As electronic devices become more and more complex, the need for greater and greater numbers of transistors on the device is increased. In addition, power consumption needs to be reduced while speed needs to be increased. At least part of the answer to these requirements involves reducing the area that each transistor occupies. However, this may adversely affect one or more of the other requirements. More specifically, as the transistors are scaled down, the gate structure is also scaled down and this increases the resistance of the gate. Hence, the power consumption is increased and the speed of the device is decreased.
Several attempts to reduce the sheet resistivity of the gate structures have been made in the past. First, the polycrystalline silicon was more heavily doped with either n-type or p-type dopants. Then, the upper portion of the gate was silicided with tungsten or titanium. Presently, cobalt silicide is being used so as to keep the resistivity down for smaller geometries. The next likely solution will involve metal gate structures.
Metal gate structures provide lower sheet resistivity virtually irrespective of the width of the gate. However, many metal gate materials have problems which must be overcome before they can be implemented in a standard semiconductor processing flow. One problem is that many metals are unstable next to SiO2, which is commonly used for the gate dielectric layer. Another problem is that many metals become less conductive when they are oxidized. It is not feasible to avoid exposing the gate structure to an oxidizing atmosphere. This is especially true if a high dielectric constant (high-k) material is used for the gate insulating layer, because most of the commonly used high-k materials require an oxygen anneal after the material is deposited. Hence, the gate material will, inevitably, be subjected to sort of oxidizing atmosphere.